See you at Hot Chips
Our team’s at Hot Chips, August 23–25 at Stanford. Before we go, why this year’s DAC was different, a write‑up from it that’s worth your time, and what we’ll be watching.

Our team will be at Hot Chips at Stanford, August 23–25. If you’re there, come say hi.
This year’s DAC was different
We spent DAC in Long Beach last month, and it was different. Investors took the stage to talk about EDA and chip startups, and the question had moved on from whether AI belongs in chip design to how it should be built.
One of the clearest reads on that came from outside the booths. Moshe Zalcberg brought four investors on stage, Shahin Farshchi of Lux Capital, Rajeev Madhavan of Radiant, Ian Clow of Samsung Catalyst Fund and Justin Shen of Lightspeed, and wrote it up in 4 VCs, Back to DAC. If you didn’t see the panel, go read it.
A few points stayed with us. The panel called this an inflection point for EDA, driven by AI and by system companies and hyperscalers designing their own chips. Rajeev argued that most AI work in design and verification so far is incremental, either tuning parameters or putting an agent around each existing tool. Shahin’s advice to founders was to go after problems the incumbents can’t solve because of how their tools are built. And Ian pointed at analog, where a small share of the blocks takes a large share of the cost.
We agree with the panel on architecture. An agent wrapped around one tool only sees what that tool sees. Tapeout is the harness around the whole flow. The agents work from one dependency graph across every tool, the tools settle every result, and Ledger keeps the history of the program in one place.
What we’ll be watching
Hot Chips is where the teams behind the year’s most ambitious chips show how they built them, and it’s the closest thing the industry has to a public design review.
We’ll spend a lot of our time in the accelerator talks, where the datapaths keep getting denser and the numerics keep getting harder to check. Shri will be in the memory and interconnect sessions, the area he’s been researching as a coauthor on CXL 3.0 memory work. Justin spent years on CPU design and verification at AMD, so expect him at every CPU talk on the schedule.
What we’re really listening for is the part most talks skip, how long it took to be sure the chip was right.
Come find us
We’re at Stanford all three days. If you work on one of these chips and want to compare notes, find us between sessions or grab time with us. And if you can’t make it, the chip we brought to DAC is still online.